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3.9.8 DC-Balanced Scrambling
A payload may contain long sequences of 1 or 0 bits. These sequences would introduce DC biases in the trans-
mitted signal, causing a non-uniform power distribution spectrum. These sequences would also degrade the per-
formance of the demodulation and data and clock recovery functions in the receiver. System performance can be
enhanced if the payload bits are randomized to reduce DC biases and increase the number of bit transitions.
As discussed above, DC-balanced data can be obtained by using Manchester encoding, which ensures that there
are no more than two consecutive 1’s or 0’s in the transmitted data. However, this reduces the effective bit-rate of
the system because it doubles the amount of data to be transmitted.
Another technique called scrambling (whitening) is widely used for randomizing data before radio transmission.
The data is scrambled using a random sequence on the transmit side and then descrambled on the receive side
using the same sequence.
The TRC105 packet handler provides a mechanism for scrambling the packet payload. A 9-bit LFSR is used to
generate a random sequence. The payload and the 16- bit CRC checksum are XOR’d with this random sequence
as shown in Figure 18. The data is descrambled on the receiver side by XORing with the same random se-
quence. The scrambling/descrambling process is enabled by setting the PKTCFG1E_Scrmb_En[4] bit to 1.
Figure 18
3.10 SPI Configuration Interface
The TRC105 contains two SPI-compatible interfaces, one to read and write the configuration registers, the other
to read and write FIFO data. Both interfaces are configured in slave mode and share the same pins: SDO (SPI
Slave Data Out), SDI (SPI Slave Data In), and SCK (Serial Clock). Two pins are provided to select the SPI con-
nection. The nSS_CONFIG pin allows access to the configuration registers and the nSS_DATA pin allows access
to the FIFO. Figure 19 shows a typical connection between a host microcontroller and the SPI interface.
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TRC105 - 05/29/13
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